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PLL650-08 - Network LAN Clock Source

Datasheet Summary

Description

The PLL 650-08 is a low cost, low jitter, and high performance clock synthesizer.

With PhaseLink’s proprietary analog Phase Locked Loop techniques, the chip accepts 25MHz crystal, and produces multiple output clocks for networking chips, and ASICs.

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Features

  • w w Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. 1 output fixed at 100MHz , 1 output fixed at 125MHz . Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 8-Pin 150mil SOIC. at . D w h S a t e e 4U m o . c.

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Datasheet Details

Part number PLL650-08
Manufacturer PhaseLink
File Size 339.01 KB
Description Network LAN Clock Source
Datasheet download datasheet PLL650-08 Datasheet
Additional preview pages of the PLL650-08 datasheet.

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Full PDF Text Transcription

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FEATURES • • • • • • • • w w Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. 1 output fixed at 100MHz , 1 output fixed at 125MHz . Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 8-Pin 150mil SOIC. at .D w h S a t e e 4U m o .c PRELIMINARY PLL650-08 Network LAN Clock Source PIN CONFIGURATION XIN XOUT GND VDD 1 2 3 4 8 7 6 5 VDD 100MHz GND 125MHz PLL 650-08 DESCRIPTIONS The PLL 650-08 is a low cost, low jitter, and high performance clock synthesizer.
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