PLL650-10 - Network LAN Clock

Product Overview

PhaseLink

Datasheet Details

Part number	PLL650-10
Manufacturer	PhaseLink
File Size	347.46 KB
Description	Network LAN Clock
Datasheet	PLL650-10 Datasheet
Additional preview pages of the PLL650-10 datasheet.

PLL650-10 Product details

Description

The PLL 650-10 is a low cost, low jitter, and high performance clock synthesizer.

With PhaseLink’s proprietary analog Phase Locked Loop techniques, the chip accepts 25MHz crystal, and produces multiple output clocks for networking chips, and ASICs.

Features

w w Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. Two outputs fixed at 125MHz. . Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 8-Pin 150mil SOIC. w . D at h S a t e e 4U . m o c.

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Other Datasheets by PhaseLink

PLL650-02 - Low EMI Network LAN Clock
PLL650-03 - Low EMI Network LAN Clock
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PLL650-07 - Low COST Network LAN Clock SOURCE
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PLL650-09 - Low Cost Network LAN Clock

Published: Feb 10, 2006 |