Part number:
PLL102-108
Manufacturer:
PhaseLink Corporation
File Size:
198.33 KB
Description:
Programmable ddr zero delay clock driver.
* PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz.
* Distributes one clock Input to one bank of ten differential outputs.
* Track spread spectrum clocking for EMI reduction.
* Programmable delay between CLK_INT and CLK[T/C] from
* 0.8
PLL102-108 Datasheet (198.33 KB)
PLL102-108
PhaseLink Corporation
198.33 KB
Programmable ddr zero delay clock driver.
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