PLL102-109 Datasheet PDF - PhaseLink Corporation Programmable DDR Zero Delay Clock Driver Specs

PLL102-109 - Programmable DDR Zero Delay Clock Driver

Datasheet Summary

Description

The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output.

Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK_INT.

Features

PLL clock distribution optimized for Double Data Rate SDRAM.

Datasheet Details

Part number	PLL102-109
Manufacturer	PhaseLink Corporation
File Size	199.76 KB
Description	Programmable DDR Zero Delay Clock Driver
Datasheet	PLL102-109 Datasheet
Additional preview pages of the PLL102-109 datasheet.

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Full PDF Text Transcription

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Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver FEATURES PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. • Distributes one clock Input to one bank of six differential outputs. • Track spread spectrum clocking for EMI reduction. • Programmable delay between CLK_INT and CLK[T/C] from –0.8ns to +3.1ns by programming CLKINT and www.DataSheet4U.com FBOUT skew channel, or from –1.1ns to +3.5ns if additional DDR skew channels are enabled. • Two independent programmable DDR skew channels from –0.3ns to +0.4ns with step size ± 100ps. • Support 2-wire I 2 C serial bus interface. • • 2.5V Operating Voltage. Available in 28-Pin 209mil SSOP.

Published: Oct 28, 2008 |