PLL103-01 - Low Skew Buffer

Datasheet Summary

Description

O O O O O I I B I P P P P SDRAM Byte0 Clock outputs.

Features

Generate 18 copies of High-speed clock inputs. Supports up to four SDRAM DIMMS synchronous clocks.
Supports 2-wire I2C serial bus interface with readback.
50% duty cycle with low jitter.
Less than 5ns delay. www. DataSheet4U. com.
Skew between any outputs is less than 250 ps.
Tri-state pin for testing.
Frequency up to 133 MHZ.
3.0V-3.7V Supply range.
48-pin SSOP package.
PIN.

PhaseLink Corporation

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Datasheet Details

Part number	PLL103-01
Manufacturer	PhaseLink Corporation
File Size	101.01 KB
Description	Low Skew Buffer
Datasheet	PLL103-01 Datasheet
Additional preview pages of the PLL103-01 datasheet.

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Full PDF Text Transcription

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PLL103-01 Low Skew Buffers FEATURES Generate 18 copies of High-speed clock inputs. Supports up to four SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50% duty cycle with low jitter. • Less than 5ns delay. www.DataSheet4U.com • Skew between any outputs is less than 250 ps. • Tri-state pin for testing. • Frequency up to 133 MHZ. • 3.0V-3.7V Supply range. • 48-pin SSOP package.

Published: Oct 28, 2008 |