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PLL103-04 - 1-to-4 Clock Distribution Buffer

Datasheet Summary

Description

The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs.

It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels.

An output enable selector is available to tri-state all outputs.

Features

  • 4 outputs identical to FIN. Low skew (< 250 ps between outputs). Input / Output frequency range 0.
  • 160 MHz 25mA drive capability at TTL levels. 70mA drive capability at CMOS levels. Output enable mode available to tri-state all outputs. www. DataSheet4U. com.
  • 3.3V operation.
  • Available in 8-Pin 150mil SOIC.
  • PIN.

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Datasheet preview – PLL103-04

Datasheet Details

Part number PLL103-04
Manufacturer PhaseLink Corporation
File Size 150.92 KB
Description 1-to-4 Clock Distribution Buffer
Datasheet download datasheet PLL103-04 Datasheet
Additional preview pages of the PLL103-04 datasheet.

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Full PDF Text Transcription

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Preliminary PLL103-04 1-to-4 Clock Distribution Buffer FEATURES 4 outputs identical to FIN. Low skew (< 250 ps between outputs). Input / Output frequency range 0 – 160 MHz 25mA drive capability at TTL levels. 70mA drive capability at CMOS levels. Output enable mode available to tri-state all outputs. www.DataSheet4U.com • 3.3V operation. • Available in 8-Pin 150mil SOIC. • • • • • • PIN CONFIGURATION FIN CLK1 CLK2 CLK3 1 8 OE^ VDD GND CLK4 PLL103-04 2 3 4 7 6 5 FIN = 0 ~ 160 Mhz Note: ^: Internal pull-up (30k Ω ) DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels.
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