2308B - 3.3V ZERO DELAY CLOCK BUFFER

Renesas

General Description

The 2308B is a high-speed phase-lock loop (PLL) clock multiplier.

It is designed to address high-speed clock distribution and multiplication applications.

The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.

Key Features

Phase-Lock Loop Clock Distribution for.

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2308B 3.3v zero delay clock buffer by Renesas - Datasheet Preview

Datasheet Details

Part number	2308B
Manufacturer	Renesas
File Size	864.28 KB
Description	3.3V ZERO DELAY CLOCK BUFFER
Datasheet	2308B Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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3.3 VOLT ZERO DELAY CLOCK MULTIPLIER DADTAATSAHSEHEETET 2308B Description The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the input clock directly drives the outputs for system testing purposes. In the absence of an input clock, the 2308B enters power down, and the outputs are tri-stated.