8P34S1102 Datasheet | Renesas

Description The 8P34S1102 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of 1PPS signals or high-frequency, very low additive phase-noise clock and data signals. The 8P34S1102 supports fail-safe operation and is characterized to operate from a 1.8V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S1102 ideal for those clock distribution applications demanding well-defined performance and repeatability. One differential input and two low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the differential device input. The device is optimized for low power consumption and low additive phase noise. Features - Two low skew, low additive jitter LVDS output pairs - One differential clock input pair - Differential CLK, n CLK pairs can accept the following differential input levels: LVDS, CML - Maximum input clock frequency: 51.2GHz - Output skew: 3ps (typical) - Propagation delay: 400ps (maximum) - Low additive phase jitter, RMS; f REF = 156.25MHz, 10k Hz- 20MHz: 34fs (typical) - Device current consumption (IDD): - 40m A typical: 1.8V - 50m A typical: 2.5V - Full 1.8V or 2.5V supply voltage - Lead-free (Ro HS 6), 16-Lead VFQFN package - -40°C to 85°C ambient operating temperature - Supports case temperature up to +105°C - Supports PCI Express Gen 1-5 Block Diagram Q0 CLK n Q0 n CLK Q1 n Q1 VREF VREF ©2022 Renesas Electronics Corporation Pin Assignment Q0 n Q0 Q1 n Q1 12 11 10 9 nc 13 nc 14 nc 15 GND 16 8 VREF 7 n CLK 6 CLK 5 VDD nc nc nc 16-lead VFQFPN 3mm x 3mm x 0.925mm package body 1.7mm x 1.7mm e Pad Size NL Package Top View June 3, 2022 8P34S1102...