9DBV0631 Key Features
- Six 1-200 MHz Low-Power (LP) HCSL DIF pairs
- DIF additive cycle-to-cycle jitter < 5ps
- DIF output-to-output skew < 60ps
- PCIe Gen5 CC additive phase jitter < 40fs RMS
- 12kHz-20MHz additive phase jitter = 156fs RMS at
- LP-HCSL outputs; save 12 resistors pared to standard
- 55mW typical power consumption in PLL mode; minimal
- Outputs can optionally be supplied from any voltage
- OE# pins; support DIF power management
- HCSL-patible differential input; can be driven by
