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HD74LV373A Datasheet

Octal D-type Transparent Latches

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HD74LV373A pdf
HD74LV373A
Octal D-type Transparent Latches with 3-state Outputs
REJ03D0331–0200Z
(Previous ADE-205-274 (Z))
Rev.2.00
Jun. 25, 2004
Description
The HD74LV373A has eight D type latches with three state outputs in a 20 pin package. When the latch enables input
is high, the Q outputs will follow the D inputs. When the latch enables goes low, data at the D inputs will be retained at
the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all
outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the
storage elements. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
VCC = 2.0 V to 5.5 V operation
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
Output current ±8 mA (@VCC = 3.0 V to 3.6 V), ±16 mA (@VCC = 4.5 V to 5.5 V)
Ordering Information
Part Name
Package Type
Package Code Package
Abbreviation
HD74LV373AFPEL
SOP–20 pin (JEITA) FP–20DAV
FP
HD74LV373ARPEL
SOP–20 pin (JEDEC) FP–20DBV
RP
HD74LV373ATELL
TSSOP–20 pin
TTP–20DAV
T
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
OE LE
D
Output Q
HXXZ
L HL L
L HHH
L L X Q0
Note: H: High level
L: Low level
X: Immaterial
Z: High impedance
Q0: Output level before the indicated steady state input conditions were established.
Rev.2.00 Jun. 25, 2004 page 1 of 10


Renesas Electronics Components Datasheet

HD74LV373A Datasheet

Octal D-type Transparent Latches

No Preview Available !

HD74LV373A pdf
HD74LV373A
Pin Arrangement
OE 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
GND 10
20 VCC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 LE
(Top view)
Absolute Maximum Ratings
Item
Symbol Ratings
Unit Conditions
Supply voltage range
Input voltage range*1
Output voltage range*1, 2
Input clamp current
Output clamp current
Continuous output current
Continuous current through
VCC or GND
Maximum power dissipation at
Ta = 25°C (in still air)*3
VCC
VI
VO
IIK
IOK
IO
ICC or IGND
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
±50
±35
±70
PT 835
757
V
V
V Output: H or L
VCC: OFF or Output: Z
mA VI < 0
mA VO < 0 or VO > VCC
mA VO = 0 to VCC
mA
mW SOP
TSSOP
Storage temperature
Tstg –65 to 150
°C
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Rev.2.00 Jun. 25, 2004 page 2 of 10


Part Number HD74LV373A
Description Octal D-type Transparent Latches
Maker Renesas
Total Page 11 Pages
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