R1QLA4436RBG Datasheet 144-Mbit DDRII+ SRAM 2-word Burst Architecture

Manufacturer: Renesas

R1QLA4436RBG 144-mbit ddrii+ sram 2-word burst architecture by Renesas - Datasheet Preview

Datasheet Details

Part number	R1QLA4436RBG
Manufacturer	Renesas
File Size	947.74 KB
Description	144-Mbit DDRII+ SRAM 2-word Burst Architecture
Datasheet	R1QLA4436RBG Datasheet

General Description

The R1QLA4436RBG is a 4,194,304-word by 36-bit and the R1QLA4418RBG is a 8,388,608-word by 18-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

It integrates unique synchronous peripheral circuitry and a burst counter.

All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K.

Overview

Datasheet R1QLA4436RBG, R1QLA4418RBG 144-Mbit DDR™II+ SRAM 2-word Burst Architecture (2.0 Cycle Read latency) with ODT R10DS0144EJ0200 Rev.2.

Key Features

Power Supply z 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ).
Clock z z z z Fast clock cycle time for high bandwidth Two input clocks (K and /K) for precise DDR timing at clock rising edges only Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems Clock-stop capability with μs restart.
I/O z z z z z z Common data input/output bus Pipelined double data rate operation HSTL I/O User programmable output impedance PLL circuitry for wide o.

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