STP5950 Description
STP5950 is the P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These device is particularly suited for low voltage application, notebook puter power management and other battery circuits where high-side switching.
STP5950 Key Features
- 100V/-15A, RDS(ON) = 36mΩ (Typ.) @VGS = -10V
- 100V/-10A, RDS(ON) = 40mΩ @VGS = -4.5V
- Super high density cell design for extremely low RDS(ON)
- Exceptional on-resistance and maximum DC current capability
- TO-220 package design ABSOULTE MAXIMUM RATINGS (Ta = 25℃ Unless otherwise noted ) Parameter Drain-Source Vo