K4M51323LC-SDN Datasheet, Samsung semiconductor

* VDD/VDDQ = 2.5V/2.5V
* LVCMOS compatible with multiplexed address.
* Four banks operation.
* MRS cycle with address key programs. -. CAS latency (1, 2 &.

ORDERING INFORMATION Part No. K4M51323LC-S(D)N/G/L/F75 K4M51323LC-S(D)N/G/L/F7L *1 Max Freq. 133MHz(CL=3), 111MHz(CL=.

The K4M51323LC is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system .