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KM48S16030 - 4M x 8Bit x 4 Banks Synchronous DRAM

Datasheet Summary

Description

The KM48S16030 is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 8 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs -. CAS Latency (2 & 3) -. Burst Length (1, 2, 4, 8 & full page) -. Burst Type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst Read Single-bit Write operation.
  • DQM for masking.
  • Auto & self refresh.
  • 64ms refresh period (4K cycle.

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Datasheet Details

Part number KM48S16030
Manufacturer Samsung semiconductor
File Size 116.77 KB
Description 4M x 8Bit x 4 Banks Synchronous DRAM
Datasheet download datasheet KM48S16030 Datasheet
Additional preview pages of the KM48S16030 datasheet.

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Other Datasheets by Samsung semiconductor
  • KM48S16030A - 128Mbit SDRAM 4M x 8Bit x 4 Banks Synchronous DRAM LVTTL
  • KM48S16030B - 128Mbit SDRAM 4M x 8Bit x 4 Banks Synchronous DRAM LVTTL
  • KM48S8030C - 2M x 8Bit x 4 Banks Synchronous DRAM
  • KM48S8030D - 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL
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Full PDF Text Transcription

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KM48S16030 4M x 8Bit x 4 Banks Synchronous DRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS Latency (2 & 3) -. Burst Length (1, 2, 4, 8 & full page) -. Burst Type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. • Burst Read Single-bit Write operation • DQM for masking • Auto & self refresh • 64ms refresh period (4K cycle) Preliminary CMOS SDRAM GENERAL DESCRIPTION The KM48S16030 is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 8 bits, fabricated with SAMSUNG′s high performance CMOS technology.
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