ST3403
DESCRIPTION
The ST3403 is the P-Channel logic enhancement mode power field effect transistor are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook puter power management and other batter powered circuits, and low in-line power loss are needed in a very small outine surface mount package.
PIN CONFIGURATION SOT-23-3L 3
FEATURE
-30V/-2.8A, RDS(ON) = 105m-ohm @VGS = -10V -30V/-2.5A, RDS(ON) = 115m-ohm @VGS = -4.5V -30V/-1.5A, RDS(ON) = 155m-ohm @VGS = -2.5V RDS(ON) =255m-ohm @VGS = -1.8V Super high density cell design for extremely low RDS(ON) Exceptional on-resistance and maximum DC current capability SOT-23-3L package design
1.Gate 2.Source
3.Drain
A3YA
1 2
Y: Year Code A: Process Code
STANSON TECHNOLOGY
120 Bentley Square, Mountain View, Ca 94040 USA TEL: (650) 9389294...
