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TC58NVG6DDJTA00 - 64 GBIT (8G X 8 BIT) CMOS NAND E2PROM

General Description

The TC58NVG6DD is a single 3.3 V 64 Gbit (77,054,607,360 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (16384 + 1280) bytes × 256 pages × 2130 blocks.

Key Features

  • Organization Device capacity Register Page size Block size.
  • TC58NVG6DDJTA00 17664 × 256 × 2130 × 8 bits 17664 × 8 bits 17664 bytes (4M + 320 K) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read Mode control Serial input/output Command control Number of valid blocks Min 2018 blocks Max 2130 blocks Power supply VCC = 2.7 V to 3.6 V Access time Cell array to register Seria.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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TOSHIBA CONFIDENTIAL TENTATIVE TC58NVG6DDJTA00 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 64 GBIT (8G × 8 BIT) CMOS NAND E PROM (Multi-Level-Cell) DESCRIPTION The TC58NVG6DD is a single 3.3 V 64 Gbit (77,054,607,360 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (16384 + 1280) bytes × 256 pages × 2130 blocks. The device has two 17664-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 17664-byte increments. The Erase operation is implemented in a single block unit (4 Mbytes + 320 Kbytes: 17664 bytes × 256 pages). The TC58NVG6DD is a serial-type memory device which utilizes the DQ pins for both address and data input/output as well as for command inputs.