ZL30112 Datasheet - Zarlink Semiconductor

SLIC/CODEC DPLL

ZL30112 Features

* November 2009

* Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input

* Provides 2.048 MHz and 8.192 MHz output clocks and an 8 kHz framing pulse

* Automatic entry and exit from freerun mode on reference fail Ordering Information ZL30112LDG1 32 Pin QFN

* Tray

ZL30112 General Description

The ZL30112 SLIC/CODEC DPLL contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SLIC/CODEC devices. The ZL30112 generates TDM clock and framing signals that are phase locked to the input reference. It helps ensure system reliability by monitoring its reference .

ZL30112 Datasheet (349.75 KB)

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Datasheet Details

Part number:

ZL30112

Manufacturer:

Zarlink Semiconductor

File Size:

349.75 KB

Description:

Slic/codec dpll.

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ZL30112 SLIC CODEC DPLL Zarlink Semiconductor

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ZL30112 Features

ZL30112 General Description

Datasheet Details

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