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ZL30116 - SONET/SDH Low Jitter System Synchronizer

General Description

12 1.1 DPLL

Key Features

  • Supports the requirements of Telcordia GR-253 and GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and the requirements of ITU-T G.781 SETS, G.813 SEC, G.823, G.824 and G.825 clocks.
  • Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64.
  • Programmable output synthesizers generate clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz.
  • Provides two DPLLs.

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Datasheet Details

Part number ZL30116
Manufacturer Zarlink Semiconductor
File Size 381.04 KB
Description SONET/SDH Low Jitter System Synchronizer
Datasheet download datasheet ZL30116 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ZL30116 SONET/SDH OC-48/OC-192 System Synchronizer Data Sheet Features • Supports the requirements of Telcordia GR-253 and GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and the requirements of ITU-T G.781 SETS, G.813 SEC, G.823, G.824 and G.825 clocks • Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64 • Programmable output synthesizers generate clock frequencies from any multiple of 8 kHz up to 77.