ZL30116 Description
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ZL30116 Key Features
- Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces u
- Programmable output synthesizers generate clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2
- Provides two DPLLs which are independently configurable through a serial software interface
- DPLL1 provides all the features necessary for generating SONET/SDH pliant clocks including automatic hitless reference s
- DPLL2 provides a prehensive set of features necessary for generating derived output clocks and other general purpose clo
- Provides 8 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2
- Pb Free Tin/Silver/Copper -40oC to +85oC
- Supports master/slave configuration for AdvancedTCATM
- Configurable input to output delay and output to output phase alignment
- Optional external feedback path provides dynamic input to output delay pensation