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ZL30119 - Low Jitter Line Card Synchronizer

General Description

12 1.1 DPLL

Key Features

  • Ordering Information June 2006.
  • Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813.
  • Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64.
  • Programmable output synthesizers (P0, P1) generate clock frequencies from any multiple of 8 kHz up to 77.76.

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Datasheet Details

Part number ZL30119
Manufacturer Zarlink Semiconductor
File Size 353.28 KB
Description Low Jitter Line Card Synchronizer
Datasheet download datasheet ZL30119 Datasheet

Other Datasheets by Zarlink Semiconductor

Part Number Description
ZL30110 Telecom Rate Conversion DPLL
ZL30111 POTS Line Card PLL
ZL30112 SLIC/CODEC DPLL
ZL30116 SONET/SDH Low Jitter System Synchronizer
ZL30117 SONET/SDH Low Jitter Line Card Synchronizer
ZL30102 T1/E1 Stratum 4/4E Redundant System Clock Synchronizer
ZL30105 T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer
ZL30107 GbE Line Card Synchronizer
ZL30108 SONET/SDH Network Interface DPLL
ZL30109 DS1/E1 System Synchronizer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ZL30119 SONET/SDH OC-48/OC-192 Line Card Synchronizer Data Sheet Features Ordering Information June 2006 • Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813 • Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64 • Programmable output synthesizers (P0, P1) generate clock frequencies from any multiple of 8 kHz up to 77.