ZL30112 - SLIC/CODEC DPLL

Product Overview

Zarlink Semiconductor

Part number	ZL30112
Manufacturer	Zarlink Semiconductor
File Size	349.75 KB
Description	SLIC/CODEC DPLL
Datasheet	ZL30112 Datasheet
Additional preview pages of the ZL30112 datasheet.

The ZL30112 SLIC/CODEC DPLL contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SLIC/CODEC devices.

The ZL30112 generates TDM clock and framing signals that are phase locked to the input reference.

November 2009.
Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input.
Provides 2.048 MHz and 8.192 MHz output clocks and an 8 kHz framing pulse.
Automatic entry and exit from freerun mode on reference fail Ordering Information ZL30112LDG1 32 Pin QFN.
Trays, Bake & Drypack.
Pb Free Matte Tin -40°C to +85°C.
Provides DPLL lock and reference fail indication.
DPLL bandwidth of 29 Hz for all rates of input references.
Less.

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Published: May 26, 2009 |