74SSTUB32868 Description
This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. One device per DIMM is required to drive up to 18 SDRAM loads or two devices per DIMM are required to drive up to 36 SDRAM loads. All inputs are SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS.
74SSTUB32868 Key Features
- 2 Member of the Texas Instruments Widebus+ ™Family
- Pinout Optimizes DDR2 DIMM PCB Layout
- 1-to-2 Outputs Supports Stacked DDR2 DIMMs
- One Device Per DIMM Required
- Chip-Select Inputs Gate the Data Outputs from
- Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line
- Supports SSTL_18 Data Inputs
- Differential Clock (CLK and CLK) Inputs
- Supports LVCMOS Switching Levels on the Chip-Select Gate-Enable, Control, and RESET Inputs
- Checks Parity on DIMM-Independent Data Inputs