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74SSTUB32865 28-BIT TO 56-BIT REGISTERED BUFFER

74SSTUB32865 Description

74SSTUB32865 www.ti.com SLAS537 * NOVEMBER 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST .
This 28-bit 1:2 configurable registered buffer is designed for 1.

74SSTUB32865 Features

* 1
* 2 Member of the Texas Instruments Widebus+™ Family
* Pinout Optimizes DDR2 RDIMM PCB Layout
* 1-to-2 Outputs Supports Stacked DDR2 RDIMMs
* Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption
* Output Edge-Con

74SSTUB32865 Applications

* of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. 2 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standar

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28-BIT 56-BIT REGISTERED BUFFER Texas Instruments
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