Datasheet Summary
D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM (Synchronous DRAM) Clock
Buffering Applications
D Output Skew, tsk(o), Less Than 250 ps D Pulse Skew, tsk(p), Less Than 500 ps D Supports up to Two Unbuffered SDRAM
DIMMs (Dual Inline Memory Modules)
D I2C Serial Interface Provides Individual
Enable Control for Each Output
D Operates at 3.3 V D Distributed VCC and Ground Pins Reduce
Switching Noise
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
D Packaged in 28-Pin Shrink Small Outline
(DB) Package
CDC319 1-LINE TO 10-LINE CLOCK DRIVER
WITH I2C CONTROL INTERFACE
SCAS590A
- DECEMBER 1997
- REVISED OCTOBER 2001
DB PACKAGE (TOP VIEW)
1Y0
1Y1
1Y...