CDCD5704 Overview
The CDCD5704 clock generator provides the necessary clock signals to support an XDR memory subsystem and Redwood logic interface using a reference clock input with or without spread-spectrum modulation. Contained in a 28-pin TSSOP package that includes four differential clock outputs, the CDCD5704 provides an off-the-shelf solution for a broad range of high-performance interface applications. The block diagram shows...
CDCD5704 Key Features
- High-Speed Clock Support: 300-MHz-667-MHz Clock Source for XDR Memory Subsystems and Redwood Logic Interface
- Quad (Open-Drain) Differential Output Drivers
- Spread-Spectrum patible Clock Input Can
- Differential or Single-Ended Reference Clock Input of 100 MHz or 133 MHz
- Serial Interface Features: Programmable Frequency Multiplier, Select Any One to Four Outputs and Mode of Operation
- All PLL Loop Filter ponents Are Integrated
- Low |Cycle-to-Cycle| of 1-6 Cycle Jitter
- 40 ps: 300-635 MHz
- 30 ps: 636-667 MHz
- PLLs Are Powered Down if No Valid REF Clock (<10 MHz) Is Detected or VDD Is Below 1.6 V