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CDCD5704 Datasheet Preview

CDCD5704 Datasheet

CLOCK GENERATOR

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Rambus™ XDR™ CLOCK GENERATOR
CDCD5704
SCAS823 – DECEMBER 2006
FEATURES
High-Speed Clock Support: 300-MHz–667-MHz
Clock Source for XDR Memory Subsystems
and Redwood Logic Interface
Quad (Open-Drain) Differential Output Drivers
Spread-Spectrum Compatible Clock Input Can
Be Distributed to Minimize EMI
Differential or Single-Ended Reference Clock
Input of 100 MHz or 133 MHz
Serial Interface Features: Programmable
Frequency Multiplier, Select Any One to Four
Outputs and Mode of Operation
Supports Frequency Multiplication Factors of:
×3, ×4, ×5, ×6, ×8, ×9/2, ×15/2, ×15/4
All PLL Loop Filter Components Are
Integrated
Low |Cycle-to-Cycle| of 1–6 Cycle Jitter:
– 40 ps: 300–635 MHz
– 30 ps: 636–667 MHz
PLLs Are Powered Down if No Valid REF
Clock (<10 MHz) Is Detected or VDD Is Below
1.6 V
Operates From Single 2.5-V Supply (±0.125 V)
Packaged in TSSOP-28
Commercial Temperature Range 0°C to 70°C
VDDP
VSSP
ISET
VSS
REFCLK
REFCLKB
VDDC
VSSC
SCL
SDA
EN
ID0
ID1
BYPASS
PW PACKAGE
(TOP VIEW)
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VDD
CLK0
CLK0B
VSS
CLK1
CLK1B
VDD
VSS
CLK2
CLK2B
VSS
CLK3
CLK3B
VDD
P0043-01
APPLICATIONS
XDR Memory Subsystem and Redwood Logic
Interface
DESCRIPTION
The CDCD5704 clock generator provides the necessary clock signals to support an XDR memory subsystem
and Redwood logic interface using a reference clock input with or without spread-spectrum modulation.
Contained in a 28-pin TSSOP package that includes four differential clock outputs, the CDCD5704 provides an
off-the-shelf solution for a broad range of high-performance interface applications.
The block diagram shows the major components of the CDCD5704, which include a phase-locked loop, a
bypass multiplexer, and four differential output buffers (CLK0 to CLK3). All four outputs can be disabled by a
logical low at the input of the EN pin. An output is enabled when EN is high and a value of 1 is in its serial
interface register (RegA–RegD).
The PLL receives a reference clock input signal, REFCLK, and outputs a clock signal at a frequency equal to the
input frequency times the multiplication factor. The PLL output clock signal is fed to the differential output buffers
to drive the enabled clocks. Disabled outputs are set to high impedance.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Rambus, XDR are trademarks of Rambus Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated




etcTI

CDCD5704 Datasheet Preview

CDCD5704 Datasheet

CLOCK GENERATOR

No Preview Available !

CDCD5704
SCAS823 – DECEMBER 2006
www.ti.com
The bypass mode routes the input clock REFCLK to the differential output buffers, bypassing the PLL.
To ensure that the CDCD5704 clock generator always performs correctly, the device switches off the PLL and
the outputs are in the high-impedance state, once the clock input is below 10 MHz. If the supply voltage VDD is
less than VPUC, all logic gates are reset, the PLL is powered down, and the outputs are in the high-impedance
state. Therefore, the device only starts its operation if these minimum requirements are met.
Because the CDCD5704 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the
PLL. With use of an external reference clock, this signal must be fixed-frequency and fixed-phase prior to the
start of stabilization time.
The device operates from a single 2.5-V supply voltage. The CDCD5704 device is characterized for operation
from 0°C to 70°C.
FUNCTIONAL BLOCK DIAGRAM
BYPASS
VDDP
VDDC
VDD
REFCLK
REFCLKB CLK0
PLL 1
300 MHz to 667 MHz
MUX
VDDP
VDDC
SDA
SCL
ID0
ID1
EN
VDD
Power
Down
Logic
Serial Interface
Control Logic
CLK0
CLk1
CLK2
CLK3
CLK0
CLK0B
CLK1
CLK1B
CLK2
CLK2B
CLK3
CLK3B
ISET
RSET
Current and Voltage
Reference
VSSP
VSSC
VSS
B0137-01
2 Submit Documentation Feedback


Part Number CDCD5704
Description CLOCK GENERATOR
Maker etcTI
Total Page 21 Pages
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