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SN65DSI86 - MIPI DSI to eDP Bridge

Description

The SN65DSI86 DSI to embedded DisplayPort (eDP) bridge

Features

  • Embedded DisplayPort™ ( eDP™) 1.4 compliant supporting 1, 2, or 4 lanes at 1.62 Gbps (RBR), 2.16 Gbps, 2.43 Gbps, 2.7 Gbps (HBR), 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps (HBR2).
  • Implements MIPI® D-PHY version 1.1 physical layer front-end and display serial interface (DSI) version 1.02.00.
  • Dual-channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1.5 Gbps per lane.
  • Supports 18 bpp and 24 bpp DSI video packets w.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.ti.com SN65DSI86 SLLSEH2C – SEPTEMBER 2013 – REVISED OSCNTO6B5EDRS2I08260 SLLSEH2C – SEPTEMBER 2013 – REVISED OCTOBER 2020 SN65DSI86 MIPI® DSI to eDP™ Bridge 1 Features • Embedded DisplayPort™ ( eDP™) 1.4 compliant supporting 1, 2, or 4 lanes at 1.62 Gbps (RBR), 2.16 Gbps, 2.43 Gbps, 2.7 Gbps (HBR), 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps (HBR2). • Implements MIPI® D-PHY version 1.1 physical layer front-end and display serial interface (DSI) version 1.02.00 • Dual-channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1.
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