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SN74AUP1G99 Datasheet Preview

SN74AUP1G99 Datasheet

LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE

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www.ti.com
SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE
WITH 3-STATE OUTPUTS
SCES594C – JULY 2004 – REVISED DECEMBER 2007
FEATURES
1
2 Available in the Texas Instruments
NanoFree™ Package
Low Static-Power Consumption
(ICC = 0.9 µA Max)
Low Dynamic-Power Consumption
(Cpd = 5 pF Typ at 3.3 V)
Low Input Capacitance (CI = 1.5 pF)
Low Noise – Overshoot and Undershoot
<10% of VCC
Input-Disable Feature Allows Floating Input
Conditions
Ioff Supports Partial-Power-Down Mode
Operation
Includes Schmitt-Trigger Inputs
Wide Operating VCC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
tpd = 7.4 ns Max at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
OE
A
B
GND
DCT PACKAGE
(TOP VIEW)
1
8
2
7
3
6
4
5
VCC
Y
D
C
DCU PACKAGE
(TOP VIEW)
OE 1
A2
B3
GND 4
8
VCC
7Y
6D
5C
YZP PACKAGE
(BOTTOM VIEW)
GND 4 5 C
B 36 D
A 27 Y
OE
1 8 VCC
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see
Figures 1 and 2).
xxxxxx
Static-Power Consumption
Dynamic-Power Consumption
(µA)
100%
(pF)
100%
80%
80%
60%
40%
3.3-V
Logic
60%
40%
3.3-V
LLoVgCic
20%
0%
AUP
20%
0%
AUP
Single, dual, and triple gates
Figure 1. AUP - The Lowest-Power Family
Switching Characteristics
at 25 MHz
3.5
3
2.5
2 Input
1.5
1
Output
0.5
0
−0.5
0
5
10 15 20 25 30 35 40 45
Time − ns
AUP1G08 data at CL = 15 pF
Figure 2. Excellent Signal Integrity
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated




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SN74AUP1G99 Datasheet Preview

SN74AUP1G99 Datasheet

LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE

No Preview Available !

SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE
WITH 3-STATE OUTPUTS
SCES594C – JULY 2004 – REVISED DECEMBER 2007
www.ti.com
DESCRIPTION/ORDERING INFORMATION
The SN74AUP1G99 features configurable multiple functions with a 3-state output. This device has the
input-disable feature, which allows floating input signals. The inputs and output are disabled when the
output-enable (OE) input is high. When OE is low, the output state is determined by 16 patterns of 4-bit input.
The user can choose the logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and
buffer. All inputs can be connected to VCC or GND.
This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition
and better switching noise immunity at the input.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
TA
–40°C to 85°C
ORDERING INFORMATION
PACKAGE (1) (2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(3)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
Tape and reel SN74AUP1G99YZPR
_ _ HY_
SSOP – DCT
Tape and reel SN74AUP1G99DCTR
H99_ _ _
VSSOP – DCU
Tape and reel SN74AUP1G99DCUR
H99_
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
2
Submit Documentation Feedback
Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G99


Part Number SN74AUP1G99
Description LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE
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