Description
The ADS6632A4A are four-bank Synchronous DRAMs organized as 524,288 words x 32 bits x 4 banks, Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Features
- JEDEC standard LVTTL 3.3V power supply.
- MRS Cycle with address key programs
-CAS Latency (2 & 3) -Burst Length (1,2,3,8,& full page) -Burst Type (sequential & Interleave).
- 4 banks operation.
- All inputs are sampled at the positive edge of
the system clock.
- Burst Read single write operation.
- Auto & Self refresh.
- 4096 refresh cycle.
- DQM for masking.
- Package:86-pins 400 mil TSOP-Type II
Ordering Information. Part No. Frequen.
ADS-663.pdf