LP621024D-T Datasheet PDF - AMIC 128K x 8-BIT CMOS SRAM Specs

LP621024D-T - 128K x 8-BIT CMOS SRAM

Datasheet Summary

Description

The LP621024D-T is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 5V power supply.

Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.

Features

Single +5V power supply.
Access times: 55/70 ns (max. ).
Current: Very low power version: Operating: 70mA (max. ) Standby: 50µA (max. ).
Full static operation, no clock or refreshing required.
All inputs and outputs are directly TTL-compatible.
Common I/O using three-state output.
Output enable and two chip enable inputs for easy.

Datasheet Details

Part number	LP621024D-T
Manufacturer	AMIC
File Size	221.95 KB
Description	128K x 8-BIT CMOS SRAM
Datasheet	LP621024D-T Datasheet
Additional preview pages of the LP621024D-T datasheet.

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Full PDF Text Transcription

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Document Title 128K X 8 BIT CMOS SRAM Revision History Rev. No. 1.1 1.2 History Add Pb-Free package type Remove non-Pb-free package type LP621024D-T Series 128K X 8 BIT CMOS SRAM Issue Date August 19, 2004 July 3, 2006 Remark Final (July, 2005, Version 1.2) AMIC Technology, Corp. LP621024D-T Series 128K X 8 BIT CMOS SRAM Features Single +5V power supply Access times: 55/70 ns (max.) Current: Very low power version: Operating: 70mA (max.) Standby: 50µA (max.) Full static operation, no clock or refreshing required All inputs and outputs are directly TTL-compatible Common I/O using three-state output Output enable and two chip enable inputs for easy application Data retention voltage: 2V (min.) Available in 32-pin DIP, SOP TSOP and TSSOP (8 X 13.

Published: Feb 17, 2020 |