MT5C1005 Datasheet - ASI

MT5C1005 SRAM MEMORY ARRAY

The Austin Semiconductor SRAM family employs high-speed, low power CMOS designs fabricated using doublelayer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, ASI offers chip enable (CE) and output enable (OE) capability. These enhancements can place the .

www.DataSheet4U.com SRAM Austin Semiconductor, Inc. 256K x 4 SRAM SRAM MEMORY ARRAY AVAILABLE AS MILITARY SPECIFICATIONS MIL-STD-883 MT5C1005 PIN ASSIGNMENT (Top View) 28-Pin DIP (C) (400 MIL) A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 CE OE Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc A6 A5 A4 A3 A2 A1 A0 NC DQ4 DQ3 DQ2 DQ1 WE 32-Pin LCC (EC) 32-Pin SOJ (DCJ) A7 A8 A9 A12 A10 A11 A13 NC A14 A15 A16 A17 NC CE OE Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 1.

MT5C1005 Features

* High Speed: 20, 25, 35, and 45 Battery Backup: 2V data retention Low power standby High-performance, low-power CMOS double-metal process

* Single +5V (+10%) Power Supply

* Easy memory expansion with CE and OE options.

* All inputs and o

MT5C1005_ASI.pdf