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AT17N040 FPGA Configuration Memory

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Description

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The AT17N series FPGA Configuration EEPROM (Configurators) provide an easy-touse, cost-effective configuration memory for Field Programmable Gate Arra.

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Datasheet Specifications

Part number
AT17N040
Manufacturer
ATMEL Corporation
File Size
205.26 KB
Datasheet
AT17N040_ATMELCorporation.pdf
Description
FPGA Configuration Memory

Features

* EE Programmable 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and
* 4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) Available as

Applications

* RESET should be programmed active Low. This document describes the pin as RESET/OE. Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and forces the

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