AS7C33128NTD18B Datasheet (Alliance Semiconductor Corporation)

AS7C33128NTD18B, 3.3V 128Kx18 Pipelined SRAM

The AS7C33128NTD18B family is a high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM) organized as 131,072 words × 18 bits and incorporates a LATE LATE Write.

This variation of the 2Mb sychronous SRAM uses the No Turnaround Delay (NTD™) architecture, featuring an enhanced Write

AS7C33128NTD18B Features

* Organization: 131,072 words × 18 bits

* NTD™ architecture for efficient bus operation

* Fast clock speeds to 200 MHz

* Fast clock to data access: 3.0/3.5/4.0 ns

* Fast OE access time: 3.0/3.5/4.0 ns

* Fully synchronous operation

* Asynchronou