AS7C33128NTD32B Datasheet (Alliance Semiconductor Corporation) - (AS7C33128NTD32B / AS7C33128NTD36B) 3.3V 128Kx32/36 Pipelined SRAM

AS7C33128NTD32B, (AS7C33128NTD32B / AS7C33128NTD36B) 3.3V 128Kx32/36 Pipelined SRAM

The AS7C33128NTD36B family is a high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM) organized as 131,072 words × 32 or 36 bits and incorporates a LATE LATE Write.

This variation of the 4Mb sychronous SRAM uses the No Turnaround Delay (NTD™) architecture, featuring an enhanced

AS7C33128NTD32B Features

* Organization: 131,072 words × 32 or 36 bits

* NTD™ architecture for efficient bus operation

* Fast clock speeds to 200 MHz

* Fast clock to data access: 3.0/3.5/4.0 ns

* Fast OE access time: 3.0/3.5/4.0 ns

* Fully synchronous operation

* Async