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AS7C33128PFD18B - 3.3V 128K x 18 pipeline burst synchronous SRAM

AS7C33128PFD18B Description

February 2005 ® AS7C33128PFD18B 3.3V 128K × 18 pipeline burst synchronous SRAM .
The AS7C33128PFD18B is a high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM) devices organized as 131,072 words × 18 bits and.

AS7C33128PFD18B Features

* Organization: 131,072 words × 18 bits
* Fast clock speeds to 200 MHz
* Fast clock to data access: 3.0/3.5/4.0 ns
* Fast OE access time: 3.0/3.5/4.0 ns
* Fully synchronous register-to-register operation
* Double-cycle deselect
* Asynchronous o

AS7C33128PFD18B Applications

* Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting BWE and the appropriate i

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3.3V 128K pipeline burst synchronous SRAM Alliance Semiconductor Corporation
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