Description
March 2001 ® AS7C33128PFD32A AS7C33128PFD36A 3.3V 128K × 32/36 pipeline burst synchronous SRAM .
The AS7C33128PFD32A and AS7C33128PFD36A are high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) devices organized as 131,072 w.
Features
* Organization: 131,072 words × 32 or 36 bits
* Fast clock speeds to 166 MHz in LVTTL/LVCMOS
* Fast clock to data access: 3.5/3.8/4.0/5.0 ns
* Fast OE access time: 3.5/3.8/4.0/5.0 ns
* Fully synchronous register-to-register operation
* Single register
Applications
* Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more bytes may be written by asserting BWE and the appropriat
