* hyper page mode operation where read and write operations within a single row (or page) can be executed at very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling edge of RAS and xCAS inputs, respectively. Al
AS4C1M16E5 Datasheet (635.37 KB)
AS4C1M16E5
Alliance Semiconductor
635.37 KB
5v 1m x 16 cmos dram.
$XJXVW
*
$6&0(
9 0î &026 '5$0 ('2 )HDWXUHV
* Organization: 1,048,576 words × 16 bits
* High speed
- 45/50/60 ns .
📁 Related Datasheet
AS4C1M16F5 5V 1M x 16 CMOS DRAM (Alliance Semiconductor)
AS4C1M16S 1M x 16 bit Synchronous DRAM (Alliance Memory)
AS4C1M16S-C 1M x 16 bit Synchronous DRAM (Alliance Memory)
AS4C1M16S-I 1M x 16 bit Synchronous DRAM (Alliance Memory)
AS4C1024 1M x 1 DRAM (Austin Semiconductor)
AS4C1259 256K x 1 DRAM (Austin Semiconductor)
AS4C1259883C 256K x 1 DRAM (Austin Semiconductor)
AS4C128M16D2A-25BCN 2Gb DDR2 (Alliance Semiconductor)
AS4C128M16D2A-25BIN 2Gb DDR2 (Alliance Semiconductor)
AS4C128M16D3A-12BIN 2Gb Double-Data-Rate-3 DRAM (Alliance Semiconductor)
