AS4C1M16E5 Datasheet - Alliance Semiconductor

AS4C1M16E5 5V 1M x 16 CMOS DRAM

Address inputs Row address strobe Input/output Output enable Write enable Column address strobe, upper byte Column address strobe, lower byte Symbol tRAC tAA tCAC tOEA tRC tHPC ICC1 ICC5 -45 45 23 10 12 75 20 155 2.0 -50 50 25 12 13 80 20 145 2.0 -60 60 30 15 15 100 Unit ns ns ns ns ns mA mA .

$XJXVW $6&0( 9 0î &026 '5$0 ('2 )HDWXUHV Organization: 1,048,576 words × 16 bits High speed - 45/50/60 ns RAS access time - 20/20/25 ns hyper page cycle time - 10/12/15 ns CAS access time 1024 refresh cycles, 16 ms refresh interval - RAS-only or CAS-before-RAS refresh Read-modify-write TTL-compatible, three-state DQ JEDEC standard package and pinout - 400 mil, 42-pin SOJ - 400 mil, 44/50-pin TSOP 2 Low power c.

AS4C1M16E5 Features

* hyper page mode operation where read and write operations within a single row (or page) can be executed at very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling edge of RAS and xCAS inputs, respectively. Al

AS4C1M16E5 Datasheet (635.37 KB)