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AS4C1M16E5 - 5V 1M x 16 CMOS DRAM

AS4C1M16E5 Description

$XJXVW  * $6&0( 9 0î &026 '5$0 ('2 )HDWXUHV * Organization: 1,048,576 words × 16 bits * High speed - 45/50/60 ns .
Address inputs Row address strobe Input/output Output enable Write enable Column address strobe, upper byte Column address strobe, lower byte Symbol.

AS4C1M16E5 Features

* hyper page mode operation where read and write operations within a single row (or page) can be executed at very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling edge of RAS and xCAS inputs, respectively. Al

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CMOS DRAM Alliance Semiconductor
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