AS7C3364PFD36B Description
February 2005 ® AS7C3364PFD32B AS7C3364PFD36B 3.3V 64K X 32/36 pipeline burst synchronous SRAM .
The AS7C3364PFD32B and AS7C3364PFD36B are high-performance CMOS 2-Mbit synchronous Static Random Access Memory (SRAM) devices organized as 65,536 word.
AS7C3364PFD36B Features
* Organization: 65,536 words × 32 or 36 bits
* Fast clock speeds to 200 MHz
* Fast clock to data access: 3.0/3.5/4.0 ns
* Fast OE access time: 3.0/3.5/4.0 ns
* Fully synchronous register-to-register operation
* Double-cycle deselect
* Asynchron
AS7C3364PFD36B Applications
* Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more bytes may be written by asserting BWE and the appropriat
📁 Related Datasheet
📌 All Tags
