Description
a SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual D.
Features
* 20 MIPS, 50 ns Maximum Instruction Rate Separate On-Chip Buses for Program and Data Memory Program Memory Stores Both Instructions and Data (Three-Bus Performance) Dual Data Address Generators with Modulo and Bit-Reverse Addressing Efficient Program Sequencing with Zero-Overhead Looping: Single-CyclApplications
* The ADSP-2104/ADSP-2109 processors are built upon a common core. Each processor combines the core DSP architectureADSP-2109 Distributors
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