ADSP-2163
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Dsp microcomputers. The ADSP-216x Family processors are single-chip microcomputers␣ optimized␣ for␣ digital␣ signal␣ processing␣ (DSP) and other high spe
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ADSP-2161 - DSP Microcomputers
(Analog Devices)
a
DSP Microputers with ROM
ADSP-216x
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture for Three-.
ADSP-2162 - DSP Microcomputers
(Analog Devices)
a
DSP Microputers with ROM
ADSP-216x
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture for Three-.
ADSP-2164 - DSP Microcomputers
(Analog Devices)
a
DSP Microputers with ROM
ADSP-216x
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture for Three-.
ADSP-2165 - DSP Microcomputers
(Analog Devices)
a
DSP Microputers with ROM
ADSP-216x
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture for Three-.
ADSP-2166 - DSP Microcomputers
(Analog Devices)
a
DSP Microputers with ROM
ADSP-216x
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture for Three-.
ADSP-2100A - DSP Microcomputers
(Analog Devices)
a
DSP Microputers with ROM
ADSP-216x
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture for Three-.
ADSP-2101 - DSP Microcomputers
(Analog Devices)
a
ADSP-2100 Family DSP Microputers
ADSP-21xx
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture fo.
ADSP-21020 - 32/40-Bit IEEE Floating-Point DSP Microprocessor
(Analog Devices)
..
a
FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 30 ns,.
ADSP-2103 - DSP Microcomputers
(Analog Devices)
a
ADSP-2100 Family DSP Microputers
ADSP-21xx
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture fo.
ADSP-2104 - Low Cost DSP Microcomputers
(Analog Devices)
a
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual D.