* 25 MIPS, 40 ns Maximum Instruction Rate (5 V) Separate On-Chip Buses for Program and Data Memory Program Memory Stores Both Instructions and Data (Three-Bus Performance) Dual Data Address Generators with Modulo and Bit-Reverse Addressing Efficient Program Sequencing with Zero-Overhead Looping: Singl
ADSP-2164 Datasheet (243.08 KB)
ADSP-2164
243.08 KB
Dsp microcomputers.
a
DSP Microcomputers with ROM
ADSP-216x
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture for Three-.
📁 Related Datasheet
ADSP-2161 - DSP Microcomputers
(Analog Devices)
a
DSP Microputers with ROM
ADSP-216x
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture for Three-.
ADSP-2162 - DSP Microcomputers
(Analog Devices)
a
DSP Microputers with ROM
ADSP-216x
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture for Three-.
ADSP-2163 - DSP Microcomputers
(Analog Devices)
a
DSP Microputers with ROM
ADSP-216x
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture for Three-.
ADSP-2165 - DSP Microcomputers
(Analog Devices)
a
DSP Microputers with ROM
ADSP-216x
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture for Three-.
ADSP-2166 - DSP Microcomputers
(Analog Devices)
a
DSP Microputers with ROM
ADSP-216x
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture for Three-.
ADSP-2100A - DSP Microcomputers
(Analog Devices)
a
DSP Microputers with ROM
ADSP-216x
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture for Three-.
ADSP-2101 - DSP Microcomputers
(Analog Devices)
a
ADSP-2100 Family DSP Microputers
ADSP-21xx
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture fo.
ADSP-21020 - 32/40-Bit IEEE Floating-Point DSP Microprocessor
(Analog Devices)
..
a
FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 30 ns,.
