CY28351 Datasheet - Cypress Semiconductor

CY28351 Differential Clock Buffer/Driver

This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential outputs levels. This device is a zero delay buffer that distributes a clock input (CLKIN) to ten differential pairs of clock outputs (YT[0:9], YC[0:9]) and one feedback clock output (FBOUT). The clock outputs are i.

CY28351 Features

* Supports 333-MHz and 400-MHz DDR SDRAM

* 60-

* 200-MHz operating frequency

* Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM applications

* Distributes one clock input to ten differential outputs

* External feedback p

CY28351-CypressSemiconductor.pdf