CY28358 Datasheet - Cypress Semiconductor

CY28358 200-MHz Differential Clock Buffer/Driver

This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential output levels. This device is a zero delay buffer that distributes a clock input CLKIN to six differential pairs of clock outputs (CLKT[0:5], CLKC[0:5]) and one feedback clock output FBOUT. The clock outputs are co.

CY28358 Features

* Up to 200 MHz operation

* Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications

* Distributes one clock input to six differential outputs

* External feedback pin FBIN is used to synchronize the outputs to the clock input

* C

CY28358-CypressSemiconductor.pdf