CY7C1347D Datasheet (Cypress Semiconductor) - 128K x 36 Synchronous-Pipelined Cache SRAM

CY7C1347D, 128K x 36 Synchronous-Pipelined Cache SRAM

This Cypress Synchronous Burst SRAM employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology.

Each memory cell consists of four transistors and two high-valued resistors.

The CY7C1347D SRAM integrate 131,072 x 36 SRAM cells with advanced synch

CY7C1347D Features

* Fast access times: 2.5 and 3.5 ns

* Fast clock speed: 250, 225, 200, and 166 MHz

* 1.5-ns set-up time and 0.5-ns hold time

* Fast OE access times: 2.5 ns and 3.5 ns

* Optimal for depth expansion (one cycle chip deselect to eliminate bus contention)