CY7C1347F Datasheet (Cypress Semiconductor) - 4-Mbit (128K x 36) Pipelined Sync SRAM

CY7C1347F, 4-Mbit (128K x 36) Pipelined Sync SRAM

1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic.

CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V.

All synchronous inputs pass through inp

CY7C1347F Features

* Fully registered inputs and outputs for pipelined operation

* 128K by 36 common I/O architecture

* 3.3V core power supply

* 2.5V/3.3V I/O operation

* Fast clock-to-output times

* 2.6 ns (for 250-MHz device)

* 2.6 ns (for 225-MHz device)