CY7C1351 Datasheet - Cypress Semiconductor

CY7C1351 128Kx36 Flow-Through SRAM

The CY7C1351 is a 3.3V, 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read.

CY7C1351 Features

* Pin compatible and functionally equivalent to ZBT™ devices IDT71V547, MT55L128L36F, and MCM63Z737

* Supports 66-MHz bus operations with zero wait states

* Data is transferred on every clock

* Internally self-timed output buffer control to eliminate the need to use O

CY7C1351_CypressSemiconductor.pdf