CY7C1353 Datasheet (Cypress Semiconductor)

CY7C1353, 256Kx18 Flow-Through SRAM

The CY7C1353 is a 3.3V 256K by 18 SynchronousFlow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

The CY7C1353 is equipped with the advanced No Bus Latency (NoBL ™) logic required to enable consecutive Read/W

CY7C1353 Features

* Pin compatible and functionally equivalent to ZBT™ devices MCM63Z819 and MT55L256L18F

* Supports 66-MHz bus operations with zero wait states

* Data is transferred on every clock

* Internally self-timed output buffer control to eliminate the need to use OE