CY7C1355C - (CY7C1355C / CY7C1357C) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

Cypress Semiconductor

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Datasheet Details

Part number	CY7C1355C
Manufacturer	Cypress Semiconductor
File Size	708.89 KB
Description	(CY7C1355C / CY7C1357C) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
Datasheet	CY7C1355C_CypressSemiconductor.pdf

CY7C1355C Product details

Description

1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.The CY7C1355C/CY7C1357C is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.This feature dramatically improves the throughput of data through the SRAM, especially in systems t

Features

No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.
Can support up to 133-MHz bus operations with zero wait states.
Data is transferred on every clock.
Pin compatible and functionally equivalent to ZBT™ devices.
Internally self-timed output buffer control to eliminate the need to use OE.
Registered inputs for flow-through operation.
Byte Write capability.
3.3V/2.5V I/O power supply.

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Other Datasheets by Cypress Semiconductor

CY7C1355A - (CY7C1355A / CY7C1357A) 256K x 36/512K x 18 Synchronous Flow-Thru SRAM
CY7C1355B - (CY7C1355B / CY7C1357B) 9-Mb (256K x 36/512K x 18) Flow-Through SRAM
CY7C135 - 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM
CY7C1350G - 4-Mbit (128K x 36) Pipelined SRAM
CY7C1351 - 128Kx36 Flow-Through SRAM
CY7C1351F - 4-Mb (128K x 36) Flow-through SRAM

Published: Oct 16, 2006 |