CY7C1392BV18 Datasheet - Cypress Semiconductor

CY7C1392BV18 - 1.8V Synchronous Pipelined SRAM

CY7C1392BV18 Features

* 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

* 300 MHz clock for high bandwidth

* 2-word burst for reducing address bus frequency

* Double Data Rate (DDR) interfaces (data transferred at 600 MHz) at 300 MHz

* Two input clocks (K and K) for precise DDR timing

* SRAM

Datasheet Details

CY7C1392BV18

Cypress Semiconductor

386.82 KB

1.8v synchronous pipelined sram.

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