CY7C1392KV18 - 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture

Cypress Semiconductor

Datasheet Details

Part number	CY7C1392KV18
Manufacturer	Cypress Semiconductor
File Size	587.97 KB
Description	18-Mbit DDR II SIO SRAM Two-Word Burst Architecture
Datasheet	CY7C1392KV18-CypressSemiconductor.pdf

18-Mbit density (2M × 8, 1M × 18).
333-MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) simplify data capture in high-speed systems.
Synchronous int.

📁 CY7C1392KV18 Similar Datasheet

CY7C131AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C131E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C136AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C136E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
CY7C1370CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
CY7C1370D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)
CY7C1371C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture (Cypress)

Other Datasheets by Cypress Semiconductor

Published: Mar 13, 2017 |