CY7C1392KV18

18-Mbit DDR II SIO SRAM Two-Word Burst Architecture

Cypress Semiconductor

* 18-Mbit density (2M × 8, 1M × 18)

* 333-MHz clock for high bandwidth

* Two-word burst for reducing address bus frequency

* Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz

* Two input clocks (K and K) for precise DDR timing

* SRAM uses rising edges

CY7C1392KV18

Cypress Semiconductor

587.97 KB

18-mbit ddr ii sio sram two-word burst architecture.

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