Datasheet4U Logo Datasheet4U.com

CY7C245A

2K x 8 Reprogrammable Registered PROM

CY7C245A Features

* Windowed for reprogrammability

* CMOS for optimum speed/power

* High speed

* 15-ns address set-up

* 10-ns clock to output

* Low power

* 330 mW (commercial) for -25 ns

* 660 mW (military)

* Programmable synchronous or asynchron

CY7C245A General Description

The CY7C245A is a high-performance, 2K x 8, electrically programmable, read-only memory packaged in a slim 300-mil plastic or hermetic DIP. The ceramic package may be equipped with an erasure window; when exposed to UV light the PROM is erased and can then be reprogrammed. The memory cells utilize p.

CY7C245A Datasheet (227.64 KB)

Preview of CY7C245A PDF

Datasheet Details

Part number:

CY7C245A

Manufacturer:

Cypress Semiconductor

File Size:

227.64 KB

Description:

2k x 8 reprogrammable registered prom.

📁 Related Datasheet

CY7C2163KV18 - 18-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)
CY7C2163KV18/CY7C2165KV18 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 18-Mbit QDR® II+ SRAM Four-Word Burst .

CY7C2165KV18 - 18-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)
CY7C2163KV18/CY7C2165KV18 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 18-Mbit QDR® II+ SRAM Four-Word Burst .

CY7C2168KV18 - 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (Cypress Semiconductor)
CY7C2168KV18/CY7C2170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 18-Mbit DDR II+ SRAM Two-Word Burst Arch.

CY7C2170KV18 - 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (Cypress Semiconductor)
CY7C2168KV18/CY7C2170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 18-Mbit DDR II+ SRAM Two-Word Burst Arch.

CY7C2245KV18 - 36-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)
CY7C2245KV18 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture .

CY7C225 - 512 x 8 Registered PROM (Cypress)
.

CY7C225A - 512 x 8 Registered PROM (Cypress Semiconductor)
1CY7C225A CY7C225A 512 x 8 Registered PROM Features • CMOS for optimum speed/power • High speed — 25 ns address set-up — 12 ns clock to output • Lo.

CY7C2262XV18 - 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture (Cypress Semiconductor)
CY7C2262XV18/CY7C2264XV18 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit QDR® II+ Xtreme SRAM Two.

TAGS

CY7C245A Reprogrammable Registered PROM Cypress Semiconductor

Image Gallery

CY7C245A Datasheet Preview Page 2 CY7C245A Datasheet Preview Page 3

CY7C245A Distributor